The invention relates to data processing systems and more particularly to an apparatus which, at a predetermined time, allows a higher priority device to intercept a channel program that is operative with a lower priority device.
2. Description of the Prior Art
A computing system may be operative with a plurality of input/output systems. The subsystem controlling the data flow is operative by means of channel programs and includes a microprocessor and a plurality of input/output devices, including but not limited to a Universal Synchronous Asynchronous Receiver Transmitter (USART) for each communication line. The microprocessor, for example, could control a USART that is operative by means of a channel program. If another communication line having higher priority requests service, the microprocessor must interrupt the channel program that is operative and switch the channel program to be operative with the requesting communication line. In the prior art the microprocessor interrupts the channel program by storing information in memory. This information stored in memory enables the channel program to continue service later on this interrupted communication line. The stored information consists of the contents of various registers in the system which must be unloaded when a higher priority communication line interrupts, and must be reloaded when the higher priority communication line has completed the data transfer and the system reverts back to the original communication line. This prior art system has the disadvantage of having to load and unload a large amount of information thereby slowing up the operation. Secondly, it is difficult to prevent the interrupt if required by the system and thirdly there is no identification of the communication line that interrupted the system.